1. Field of the Invention
The present invention relates to a semiconductor device which includes, between an external connection terminal and an internal circuit region, an ESD protection element for protecting an internal element formed in the internal circuit region against breakdown from ESD.
2. Description of the Related Art
In semiconductor devices that include MOS transistors, it is a known practice to install an “off” transistor as an ESD protection element for preventing the breakdown of an internal circuit due to static electricity from an external connection PAD. The “off” transistor is an NMOS transistor that is kept in an off state by fixing its gate electric potential to a ground voltage (Vss).
To prevent the ESD breakdown of an internal circuit element, it is important to draw as large a ratio of ESD pulses as possible into the off transistor while inhibiting ESD pulses from propagating to the internal circuit element, or to convert a fast, large ESD pulse into a slow, small signal before transmitting the pulse.
The off transistor is often set to a wide transistor width (W width) on the order of several hundreds microns because, unlike other MOS transistors that constitute internal circuits such as a logic circuit, the off transistor needs to let a large amount of electrostatic current that has been drawn in flow through at once.
The off transistor therefore takes up a large area, which poses a problem particularly in a small-sized IC chip by increasing the overall cost of the IC.
A common form of the off transistor is a comb-shaped combination of a plurality of drain regions, source regions, and gate electrodes. However, the structure which is a combination of a plurality of transistors makes it difficult to ensure that all parts of the ESD protection NMOS transistor operate uniformly, which can lead to a concentration of current in, for example, a place at a short distance from the external connection terminal and allows a breakdown without giving the ESD protection NMOS transistor a chance to fully exert its intended ESD protection function.
A remedy for those problems has been proposed in which transistor operation is quickened in accordance with the distance from the external connection terminal by setting the distance between a contact hole and a gate electrode, particularly in a drain region, progressively shorter as the distance from the external connection terminal increases (see JP 07-45829 A, for example).
However, reducing the W width in an attempt to reduce the area that the off transistor takes up renders the off transistor incapable of implementing its protection function satisfactorily. The proposed remedy, in which the transistor operation speed is adjusted locally by adjusting the distance from a contact hole to a gate electrode in a drain region, also has additional problems including a failure to secure a desired contact width due to the reduced drain region width, and a chance that adjusting the distance from the contact hole to the gate electrode alone is not enough to deal with the further increased surge propagation speed which has been brought about in recent years by the development of wiring containing high-melting point metal and the resultant lowering of wiring resistance. Moreover, the proposed remedy does not disclose a measure for preventing the ESD breakdown of an internal circuit element by allowing the off transistor to operate on a voltage lower than that of the internal circuit element and by drawing as large a ratio of ESD pulses as possible into the off transistor while inhibiting the propagation of ESD pulses to the internal circuit element.